1. Field of the Invention
The present invention relates to semiconductor memory devices. More particularly, the present invention relates to an embedded DRAM (Dynamic Random Access Memory) having a high bandwidth.
2. Description of the Background Art
In recent years, the significant improvement in the performance of the computer system such as the operating speed based on a CPU has induced the intensive demand for improving the bandwidth even for DRAMs. In general, the bandwidth is defined by the following equation (1). EQU Bandwidth=number of data bus lines.times.operating frequency of data bus (1 )
In order to increase the bandwidth, the number of lines of the data bus (bus width) must be increased. Alternatively, the operating frequency of the data bus must be increased by fabricating a chip according to a process technique that allows fabrication of a transistor of superior characteristics. However, both approaches are costly and implementation thereof is not easy. This is because improvement in performance is always carried out under the trade off between performance and cost.
In some microprocessors, the method of increasing the operating frequency of the data bus is effected by providing a pipeline register as a relay. However, in a DRAM, the data signal of a memory cell and the data signal amplified by a sense amplifier are both so weak that a bidirectional and complementary type input/output data bus is generally employed for the sense amplifier.
Referring to FIG. 12, a conventional typical embedded DRAM includes a dynamic memory cell array (DMCA) 100 divided into four banks #1-#4, row decoders 101(#1)-101(#4) provided corresponding to banks #1-#4, respectively, column decoders 102(#1)-102(#4) provided corresponding to banks #1-#4, respectively, sense amplifier groups SA(#1)-SA(#4) provided corresponding to banks #1-#4, respectively, a static memory cell array (SMCA) 200 functioning as a cache memory, bidirectional read/write buses 1030(#1)-1030(#4) connected between sense amplifier groups SA(#1)-SA(#4) and static memory cell array 200, and a bidirectional read/write bus 2000 connected between static memory cell array 200 and an external pin (not shown).
Bidirectional and complementary type read/write buses 1030(#1)-1030(#4) are employed in the conventional embedded DRAM. Although not shown, there may be another amplifier provided immediately preceding static memory cell array 200 since the data signal output from sense amplifier groups SA(#1)-SA(#4) is weak. Even if the path from the amplifier to the external pin could be pipelined, it was difficult to pipeline the bidirectional and complementary type read/write bus per se.
Thus, in order to increase the bandwidth of a DRAM, the method of increasing the number of lines of read/write buses 1030(#1)-1030(#4) or slightly increasing the operating speed of the entire DRAM was taken. It was difficult to significantly increase the number of read/write buses 1030(#1)-1030(#4) since they are generally arranged on a shunt region of the word line.
Various DRAMs having a high bandwidth have been proposed. However, none exhibit definite improvement in the average or worst case bandwidth despite their higher peak of the bandwidth. For example, in a synchronous DRAM, the bandwidth is 800 Mbytes/seconds for the best case and 114 Mbytes/seconds for the worst case.
In the field of a DRAM for a frame buffer, there is a method of dividing the memory cell array into a plurality of banks in order to reduce the page miss rate. When random access is effected over a plurality of banks in a DRAM having one column decoder provided in common to a plurality of banks, the access speed was limited to 20 nano seconds at most. High speed random access over a plurality of banks is allowed in a DRAM having a column decoder and a bank provided in a one-to-one correspondence. However, the penalty in silicon by the column decoder is great.
Problems in conventional art are summarized as follows.
(1) A greater number of data bus lines for the purpose of increasing the bandwidth causes increase in silicon penalty.
(2) A greater number of banks for the purpose of reducing the page miss rate causes increase in silicon penalty.
(3) Usage of a DRAM as a frame buffer causes increase of page miss in CRT refresh.